1. Field of the Invention
The present invention is directed to a solid-state relay, and more particularly to a solid-state relay having a pair of LDMOSFETs of which drains define output terminals for connection with a load to be controlled by the relay.
2. Description of the Prior Art
Solid-state relays have been widely utilized in place of mechanical relays in view of many advantages including miniaturized configuration, low-energy consumption, and high-speed switching performance. Because of the above advantages, the solid-state relay can be successfully incorporated in a small device, such as an automatic test equipment for testing LSI chips, for example. When utilized for the measurement of this kind, the relay is designed to provide a series of output signal as a testing signal. As the frequency of the output signal becomes higher, the relay is required to have a lower output capacitance developed across output terminals of the relay during off-periods of the output signal, i.e., the periods in which the output terminals are in non-conductive condition, in addition to minimizing on-state resistance between the output terminals during on-periods of the output signal. The output capacitance is the sum of a drain-source capacitance and a gate-drain capacitance at the non-conductive condition of the output terminals of the relay.
Japanese Patent Laid-Open Publication No. 9-312392 discloses a solid state relay which utilizes LDMOSFETs as switching elements in an attempt to reduce the output capacitance. The LDMOSFET has structure in which a well region and a drift region are diffused in the top surface of a silicon layer with a source region being diffused within a confine of the well region and with a drain region being diffused within a confine of the drift region. However, since the drift region and the well region are formed in the top surface of the silicon layer, there is formed a P-N interface of extended area including the bottoms of the drift region and the well region. The P-N interface of such enlarged area is responsible for increasing a capacitance between the source and drain of LDMOSFET. Accordingly, the LDMOSFET of this structure is not satisfactory for minimizing the output capacitance between the output terminals of the relay.